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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst READ Command
Figure 29: READ Output Timing – t DQSCK (MAX)
CK#
RL - 1
RL
t CH
t CL
RL + BL/ 2
CK
DQS#
DQS
t LZ(DQS)
t DQSCKmax
t RPRE
t QH
t DQSQmax
t HZ(DQS)
t RPST
t QH
t DQSQmax
DQ
D OUT
D OUT
D OUT
D OUT
t LZ(DQ)
t HZ(DQ)
Transitioning data
Notes:
1. t DQSCK can span multiple clock periods.
2. An effective burst length of 4 is shown.
Figure 30: READ Output Timing – t DQSCK (MIN)
CK#
RL - 1
RL
t CH
t CL
RL + BL/2
CK
DQS#
DQS
t LZ(DQS)
t RPRE
t DQSCKmin
t QH
t DQSQmax
t HZ(DQS)
t RPST
t QH
t DQSQmax
DQ
D OUT
D OUT
D OUT
D OUT
t LZ(DQ)
t HZ(DQ)
Transitioning data
Note:
1. An effective burst length of 4 is shown.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
56
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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